An Ultra-Wide Band Monopole Eclipse Antenna
Akshay Gore
Abstract
In this paper a monopole eclipse antenna is presented. The proposed antenna was simulated using Computer Simulation Technology (CST) and HFSS Package. The performance parameters like return loss of the single antenna as well as transmission function, group delay are calculated. Good ultra wide band performance is achieved.
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Application of Artificial Neural Network and Response Surface Methodology for Achieving Desired Surface Roughness in End Milling Process of Ductile Iron Grade 80-55-06
Anuj Kumar Sehgal, Meenu
Abstract
Manufacturability is an attribute which indicates how economically a component can be machined to meet the specified requirements. This concept embraces the traditional indicators of machinability from the customer and manufacturer’s perspective viz. surface roughness (Ra), metal removal rate (MRR) etc. Ductile Iron being a family of materials which offers the wide range of properties obtained through micro-structural control. In this study, the modeling and optimization of surface roughness in CNC end milling of Ferritic-Pearlitic Ductile Iron Grade 80-55-06 is conducted, taking into account the parametric effect of spindle speed, feed rate and depth of cut. Central composite design (CCD) is employed in developing an efficient second-order response surface mathematical model. Two methods, response surface methodology (RSM) and artificial neural network (ANN) are used for optimized prediction of surface roughness. Analysis of variance (ANOVA) is used to test the adequacy of the developed mathematical model. Further, ANN analysis with multilayer feed forward perceptron structure using graphical user interface (GUI) under MATLAB is adopted with the experimental values as input-output pairs. Finally, efficiency of different transfer functions with number of neurons in hidden layers is compared with the results obtained through response surface methodology (RSM). The results indicated that the artificial neural network (ANN) model predicts with higher accuracy compared with response surface methodology (RSM). TANSIG training transfer function along with PURELIN output transfer function is found to be the most appropriate training transfer function to model for surface roughness.
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IPv4/IPv6 Transition Expenses Paradigm using a Node Multi Homing Approach (Multihmcost6)
Hanumanthappa J. , Manjaiah D. H.
Abstract
This research paper pinpoint on one of the 20th century very popular communications protocols that located at the heart of an Internet the Internet Protocol(IP), which allows data and other traffic to roam the Internet and to arrive at the desired destination. In this innovative research work we estimated and investigated an economical and technological IPv4/IPv6 a novel node multi homing transition expenses model named Multihmcost6. The process of deploying IPv6 looks like a complex and expensive operation, however careful planning and choosing the right technique actually converts the transition to IPv6 smooth and easy. Moving from IPv4 to IPv6 is not so easy, straight forward, and ideas to simplify the migration between the two versions have to be standardized. The Multihmcost6 prototype of IPv4/IPv6 node multi homing approach can speed up the IPv4/IPv6 migration faster and however the overall migration cost is either relatively low, medium or high depending on our assumptions and basic requirements. This research paper provides an analysis of the potential benefits of IPv6, as compared to IPv4. It also outlines the principal direct and indirect expenses that entities will likely incur to deploy IPv6 in a node multi homing approach. The Multihmcost6 supports an economical and technological expenses prediction and estimation graph with the following important points such as 1)An Actual rate of Hardware which specifies an economical value. 2)Real expenses of Software and an Operating Systems costs. 3)Labour outlay. 4)An Un anticipated charge and 5)An another cost. This paper discusses and highlights the role and status of Multihmcost6 and also how multihmcost6 approach can increase the IPv4/IPv6 node multi homing transition type faster and also to determine whether the migration mechanism takes place in a very soft and smooth manner. This research article also considers concepts and ideas related to the interoperability of an IPv4 protocol and an IPv6 protocol devices and networks across national borders.
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Evaluation of Cache Memory Parameters with Different Instruction Set Architectures
N. Ramasubramanian, Hathiram Banoth and P.S. Tamizharasan
Abstract
Latest advancements in multi-core have created interest among many research groups in exploring and finding out ways to harness the true power of large number of processor cores. Therefore, multi-core systems have become the dominant architecture for desktop, high-performance and handheld devices. Several chip manufacturers including AMD, IBM, Intel and Sun have released systems, which have multiple processing units on a single chip. This trend is likely to continue with more and more cores being put on a single chip. However, these architectures have introduced many challenges in maximizing the application performance. Thus, performance evaluation of the multi-core architectures becomes very important to unveil the potential of these systems. In order to analyse the experimental results better, an architectural overview of the experimental test-bed is provided. In addition, experimental methodology and the targeted performance metrics are described. Cache memory read latency is measured for varying memory sizes up to 8MB for 64-bit stride memory accesses. The entire memory hierarchy is measured starting from the L1 cache to the main memory. Results of M5sim conducted on AMD Opteron 2218 shows a reduced access time compared to the results obtained from ALPHA ISA, AMD Opteron 2218 shows the better performance than ALPHA 21264(EV 6).
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Evolutionary Hybrid Genetic-Firefly Algorithm for Global Optimization
Shaik Farook, P. Sangameswara Raju
Abstract
The paper presents the Evolutionary Hybrid Genetic-Firefly algorithm for the optimization of complex problems and to search global solution more precisely. In this algorithm the idealized rules of the firefly algorithm i.e. swarm behaviour is combined together with the evolutionary strategy, i.e. the survival of the fitness strategy of the genetic algorithm to evolve a Hybrid algorithm. In the hybrid evolution the genetic algorithm searches the solution space for global minimum and the Firefly algorithm improves the precession of the potential candidate solution. The proposed strategy was implemented on various benchmarking test functions to evaluate the general performances of the individual algorithms and Hybrid Genetic-Firefly algorithm in terms of rate of convergence, precession and robustness to find the global best solution. The simulation results clearly illustrate that the proposed strategy is very effective in finding the global solution precisely
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Hardware Implementation of Neural Network based Fault Classifier System of CRO
Ritu Munjal, Sandeep Kumar
Abstract
This paper deals with design and implementation of fault classifier of Cathode Ray Oscilloscope. The system is modeled with eight symptoms and thirteen faults. Each symptom has specified faults. The feed forward neural network based system is simulated in MATLAB. After simulation, the hardware implementation of neural network based system is done on CPLD board for which the HDL code is simulated, synthesized, and implemented.
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Harmonization of Indian Accounting Practices with IFRS- Analysis in terms of Cash flow Predictability and Persistence
Shobana Swanynathan, Sindhu
Abstract
India is in its nascent stage of implementing IFRS and few companies in India had already started to adopt IFRS. The presentation of financial statement by firms in India is governed by Accounting Standard 5 and Schedule VI of the companies Act 1956. In the process of harmonization with IFRS, India had revised the schedule VI in the light of IAS 1 and other International Accounting Standards effective from 1st April 2011. This paper is an attempt to compare the accounting quality measured in terms of cash flow predictability and cash flow persistence of Indian firms before and after the implementation of the revised schedule VI in preparing their financial statement.
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Image Authentication Scheme using Digital Signature and Digital Watermarking
Seyed Mohammad Mousavi
Abstract
Usual digital signature schemes for image authentication encode the signature in a file separate from the original image, so this process require extra bandwidth to transmit it. Meantime, watermarking is an information hiding sub-discipline that embeds some information into host image. In this paper a joined digital signature and digital watermarking scheme for image authentication is proposed which is based on signature generation method purposed and combined DWT-DCT watermark embedding procedure. The scheme extracts signature from the original image and embeds them back into the image as watermark which leads to avoiding additional signature file.
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Improving Performance of Real Time Scheduling Policies for Multicore Architecture
N. Ramasubramanian, Ashutosh, Akhilesh Kumar Verma, Manvendra Singh and Praveen Kumar Yadav
Abstract
Increase in demand of multicore for embedded systems has lead to the need of efficient real time scheduling policies. In this paper a new implementation for global EDF is proposed for scheduling in multicore systems. It uses a heap global data structure to speed-up scheduling decisions. Ready tasks are enqueued in a logical global queue, and the M highest priority tasks are selected to run on the M cores. The logical global queue is implemented using a set of distributed run-queues, one for each core. Each run-queue is implemented using a linked list. The max heap is used for keeping track of deadlines of the earliest deadline tasks currently executing on each run queue. Deadlines are used as keys and if B is a child node of A, then deadline (A) <=deadline (B). Therefore, the node in the root directly represents the CPU where the tasks need to be pushed. Node of the heap is implemented using the structure data structure. The average total turnaround time and percentage of tasks completed is analyzed as the number of cores increases for some task set. The performance of different processor cores is compared based on percentage of tasks completed.
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Software Testing using Morkov Chain usage Model
Raj Kumari
Abstract
Model base testing is the application of model base design and optionally also executing artifact to perform Software testing .Model can be used to represent the desired behavior of a system under test(SUT) or represent testing strategies and a test environment. A model describing SUT is usually an abstract, partial presentation of the system under test desired behavior. Test cases derived from such a model are functional test on the same level of abstraction as the model. The test cases are collectively known as abstract test suite. Software testing is to be an expensive yet integral of the software development life cycle(SDLC). Testing enable the developer to verify the product and provide the mean for and user to validate the system according to their needs. The choice of software modeling methods depends on the types of testing to be performed on the system .Testing are performed during the designed phase of a software project. The goal of all software testing is to improve the quality of software product by uncovering as many faults as possible within the allocated time.
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Performance Analysis and Optimization of Low Power SRAM
Rashmi Sharma, Anshuman Singh, V. K. Pandey
Abstract
The demand for Static Random Access Memory (SRAM) is increasing with large use of SRAM in system on-chip and high performance VLSI circuits. This paper focuses on the dynamic power dissipation during the Write operation in CMOS SRAM cell. Charging and discharging of bit lines consume more power during the Write “1” and Write “0” operation. Today’s microprocessors are very fast and require fast caches with low power dissipation. In this paper the 8T SRAM cell, includes two more trail transistors in the pull down path for proper charging and discharging the bit lines. Due to this it consumes less power, delay and short circuit power during write operation. The 8T SRAM cell designed and optimized using Tanner Tool. Schematic of the SRAM cell is designed on S-Edit and Net list Simulation done by using T-Spice and waveforms are analyzed through W-EDIT. The circuit is characterized by using the 130nm technology which is having supply voltage of 1.5volt.The results of 8T SRAM cell is compare with conventional 6T SRAM. This paper optimize low power 8T SRAM which reduce power and delay during Write operation
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Analysis of Digital Watermarking using full Counter Propagation Neural Networks and Hopfield Model
Amarjeet Kaur, Supreet Singh
Abstract
Digital Watermarking offers techniques to hide watermarks into digital content to protect it from illegal copy or reproduction. Existing techniques based on spatial and frequency domain suffer from the problems of low Peak Signal to Noise Ratio (PSNR) of watermark and image quality degradation in varying degree. In earlier papers, the author proposed only the watermark was embedded and extracted through specific fcnn technique. In this paper, we propose Hopfield model and full counter propagation neural network (fcnn) techniques to overcome the remedies such as peak signal to noise ratio (psnr) and to maintain the quality of the image. We also calculate the psnr and normal correlation by adding the white Gaussian noise.
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DCT Based Scene Break Detection for Color Video using Variance of Histogram Difference of DC Image
Rakesh Trivedi, Mehul Shah and Laukik Patel
Abstract
In current digital environment video is important parameter for interactive multimedia. In this article we propose new method for detection of scene breaks in color video using variance of histogram difference of consecutive DC images. DC image concept is used for analysis to reduce processing time.DCT is used for compression of color video. Simulation results shows how quickly and efficiently this algorithm detects cut regions in video frame sequences.
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A Study on Customer Perception on Retail Services in Select Organized Retail Stores in Semi-Urban Areas
(A Case Study in Kadapa City, A. P.)
E. Sunil Kumar, M. Sudhir Reddy
Abstract
The performance of the retailing sector for the past few years is outstanding and witnesses a huge revamping exercise, significantly contributed by the growth of the organized retailing. Rapid urbanization, exposure to large number of foreign brands and changing lifestyle and preferences has contributed to the growth of retailing in India. This study on customer perception on retailing services aims to identify the dimensions in which the services provided by the organized retail outlets to the customers and also it revels the dimensional measure and the perception of the customers. Further this study explores the factors that derive the perception of the customers on services in organized retail.
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Role of Family Support in Balancing Personal and Work Life of Women Employees
S. Padma, M. Sudhir Reddy
Abstract
The Economy and Financial needs of the Family made the women to come out the home and work for livelihood. They try to perform various jobs and sometimes may opt for the difficult jobs in order to satisfy the above need. The present study was on Female Police Personnel which was conducted in Andhra Pradesh State Police Department, AP, India particularly on Women Police Constables and Head Constables. The study has aimed to find the impact of family Support on Work life Balance. Children age category, Elder parents’/in-laws health care on Work Life Balance of Women Employees are also included in the study. Various Statistical tools were used to meet the above mentioned objectives. The results revealed that Women with the responsibility of elder parents’ health need to be given a helping hand to balance their personal and professional works.
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